Information can be retained in non-volatile memories employing various physical mechanisms such as storage of charge in conductive or dielectric layer in so-called flash memories, re-arrangement of charge in a crystal in so-called FeRAM memories. One type of non-volatile memories is phase-change memories (PCM) also known as phase-change RAM (PRAM). Here information is stored in a memory cell by changing the physical state (amorphous/crystalline) or crystal phase of a phase change material and hence its resistivity. When used in a memory cell, the phase of the phase change material is typically changed by locally heating the material by means of a small pulse of electrical power. Typically a PCM cell comprises two contacts for contacting a layer of a phase change material. When sufficient current is flowing from one contact to another contact through this phase change material layer, this layer will be locally heated resulting in a local change of the solid state thereof. The PCM cell is said to be programmed. Depending on the solid state obtained, e.g. amorphous or crystalline, a bit is either written or erased.
Several configurations of PCM cells can be distinguished in the prior art, depending on the relative position of the phase change layer and the contacts. In a horizontal PCM cell the current flows in an essential horizontal direction through the phase change material, i.e. substantially parallel to the substrate upon which the PCM cell is formed. The footprint of such a horizontal PCM cell is at least the area of the spaced apart contacts and the area of the phase change material in-between these contacts. To allow aggressive scaling and hence reduction of the footprint of an individual memory cell, PCM cells can be configured in a vertical way. State-of-the-art vertical PCM cells consist of a layer of phase change material sandwiched between a top contact, also known as top electrode, and a bottom contact, also known as bottom electrode. The bottom contact is often labeled heater. Such vertical PCM cells are disclosed by A. Pirovano et al. in “Low-Field Amorphous State Resistance and Threshold voltage Drift in Chalcogenide Material”, IEEE Trans. Elect. Dev. Vol. 51 no. 5 May 2004 p. 714 and by S. Lai and T. Lowrey in “OUM—A 180 nm Nonvolatile Memory Cell Element Technology for Stand Alone and Embedded Applications”, proceedings of IEDM 2001, p 36.5.1-36.5.4. The footprint of a vertical PCM cell and hence the density of the corresponding memory array, is at least the area of the interface between the bottom electrode and the phase change material. This interface region is of the order of F2, whereby F is the minimal dimension available in a given semiconductor manufacturing process. Typically the area of the interface region between the bottom electrode and the phase change layer is smaller than the area of the interface region between the top electrode and phase change layer. For a given current, the current density will consequently be the largest at the bottom electrode/phase change material interface. This location is labeled the melting spot (11) or hot spot as in this region the phase change material will first melt due to the Joule heating and the change in crystallographic structure of the phase change material will start. FIG. 1 shows a schematic cross-sectional view and an electrical equivalent scheme of a typical vertical PCM memory cell formed on a substrate (not shown). The vertical PCM memory cell (1) comprises a select transistor (3) and a PCM element (2) stacked on top of it. The select transistor in this example is a vertical p-n-p bipolar transistor. The n-type base (9) of the bipolar transistor (3) is connected to the word line (WL) of a memory matrix of which the memory cell is an element, while the p+ emitter (10) is connected to the bottom electrode (5). The p+ collector (8) is grounded. The bottom electrode (5) is formed of a conductive material, such as a metal, embedded in a dielectric layer (4), also known as Inter Layer Dielectric (ILD). This dielectric layer (4) isolates the phase change material (6) from the select transistor (3). Overlying the bottom electrode (5) is a layer of phase change material (6). On top of the phase change material a top electrode (7) is formed which is connected to the bit line (BL) of the corresponding memory matrix. As can be seen in FIG. 1 the interface between this top electrode (7) and the phase change material (6) can be substantially larger than the interface between the bottom electrode (5) and the phase change material (6). The amount (11: within dotted line) of the phase change material which will be affected by the Joule heating and hence the programmable volume (11) is determined by the area of the bottom interface. The area of this bottom interface corresponds to the cross-sectional area of the bottom electrode (5) perpendicular to the current path (arrow) and hence is determined by the layout of the bottom electrode.
One drawback of the prior art vertical PCM memory cells is the high writing current, being typically of the order of 1 to 10 mA. Apart from power consumption, such high writing current impedes the formation of high density memory cells as bipolar transistors need to be used as select transistor capable of providing such high writing currents instead of MOSFET transistors which are more easily to integrate and to scale. To lower this writing current, the heat dissipation from the melting spot (11) should be limited. Several solutions are known in the art.
One can lower the heat dissipation by choosing a material for the bottom electrode which has a lower thermal conductivity. Table 1 below lists materials used to manufacture vertical PCM cells. From this table one would select TiN to form the bottom electrode (5) as its thermal conductivity is less than the thermal conductivity of TaN or TiAlN. Depending on the material choice for the bottom electrode the writing current can be significantly decreased.
Also, alternative configurations have been proposed to limit the area of the bottom interface and to confine the current, inter alia in U.S. Pat. No. 5,406,509, by C. W. Jeong et al. in “Switching Current Scaling and Reliability Evaluation in PRAM”, proceedings of the Non-Volatile Semiconductor Memory Workshop, 2004, 29-29, and by S. L. Cho et al. in “Highly Scalable On-axis Confined Cell Structure for High Density PRAM beyond 256 MB” in the proceedings of the 2005 VLSI symposium p 96-97. FIG. 2 shows an example of such confined vertical PCM memory cell. On top of the bottom electrode (5) a dielectric layer is deposited (12). In this dielectric layer (12) an opening (13) is formed to expose the underlying bottom electrode (5). A layer of phase change material (6) is formed overlying this opening (13). Typically SiO2 is used as dielectric material as it provides a confinement of the electrical current and thermal energy to the volume defined within the opening (13). In order to fill the opening (13) with the phase change material, a sequence of in-situ deposition and etch steps is used to deposit the phase change material (6) in the opening (13). In this deposition/etch sequence, each deposited layer is partially etched back using an anisotropic etch to accommodate for the non-conformal character of the deposition process and to improve the filling of the opening (13). Typically a thick dielectric layer (12) of 100 nm of SiO2 is deposited over the bottom electrode (5) in which an opening (13) having a diameter of about 50 nm is patterned. Phase change material 6) is deposited at least in this opening (13). This configuration allows decreasing the writing current by a factor of 2.
Although the confined vertical PCM memory cell concept helps reducing the writing current, several problems remain. A first problem in such a confined configuration is that the dimensions of the opening (13) can not be well controlled as the aspect ratio, i.e. the ratio height/diameter, is typically >1. This lack of dimension control will result in a statistical spread of the dimensions of the melting spot. Especially a wide range of contact resistance distribution inevitably leads to a wide spread of the writing current as is shown by S. J. Ahn et al. in “Highly manufacturable high density phase change memory of 64 Mb and beyond” in the proceedings of IEDM 2004 p 907-910 and by Y. N. Hwang et al. in “Writing current reduction for high-density phase-change RAM” in the proceedings of IEDM 2003 p 37.1.1-37.1.4. A second problem is that the etch-back step in the sequence of deposition/etch/deposition technique for conformal deposition of the phase change material in the opening (13) is likely to induce damages in the active region (11), i.e. the melting spot, of this phase change material, resulting in bad characteristics as is shown by S. J. Ahn et al. in “Highly manufacturable high density phase change memory of 64 Mb and beyond” in the proceedings of IEDM 2004 p 907-910 and by S. H. Lee et al. in “Full integration and cell characteristics for 64 Mb nonvolatile PRAM” in the proceedings of 2004 VLSI symposium p. 20-21. A third problem is that in this confined configuration the active region (11) is in direct contact with the bottom electrode (5), allowing heat dissipation through this bottom electrode. Consequently less heat will be available for melting of the phase change material. A fourth problem is that this direct contact of the active region (11) with the bottom electrode (5) might result in a limited endurance of PCM memory cells. After typically less than a billion cycles of amorphization and re-crystallization, the phase change material remains in a given phase, either crystalline or amorphous, and the cell can no longer be programmed.
Hence there is a need for a vertical PCM memory cell which overcomes the problems of the prior art vertical PCM memory cells, in particular the problems mentioned in this background section.